
25AA640A/25LC640A
FIGURE 1-1:
CS
HOLD TIMING
16
17
16
17
SCK
18
1 9
SO
n+2
n+1
n
High-Impedance
n
n-1
Don’t Care
5
SI
n+2
n+1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
Mode 1 , 1
7
8
3
12
11
SCK Mode 0 , 0
5
6
SI
SO
FIGURE 1-3:
CS
MSB in
High-Impedance
SERIAL OUTPUT TIMING
LSB in
SCK
SO
9
MSB out
10
13
14
3
15
ISB out
Mode 1 , 1
Mode 0 , 0
SI
? 2003-2012 Microchip Technology Inc.
Don’t Care
DS21830E-page 5